As integrated circuit devices become more highly integrated, it may be increasingly difficult to form gate electrodes and conductive contacts for the devices. For example, as a semiconductor memory device becomes more highly integrated, the structure of a memory cell generally becomes more complicated. A memory cell of a highly integrated dynamic random access memory (DRAM) device generally comprises a pass transistor and a capacitor. A high performance capacitor is formed in a defined area in order to reduce the soft error rate (SER) and enhance the operational characteristics of the cell at low voltages. Thus, capacitor-over-bitline (COB) structures have been developed, where a capacitor is formed on a bitline in order to form the high performance capacitor.
In a memory cell of the COB structure, the bitline should be connected to a drain region (or a source region) of the pass transistor, and the storage electrode of the capacitor should be connected to a source region (or a drain region) of the pass transistor. In order to connect different conductive layers to each other, a bit line contact hole and a storage electrode contact hole should be formed on the drain region of the pass transistor and the source region thereof, respectively.
Unfortunately, as the DRAM device becomes more highly integrated, the bit line or the storage electrode contact hole may become narrower and deeper. Therefore, the contact resistance may increase. The process margin which prevents misalignment of the contact hole may also be reduced during the photolithography process for forming the contact hole, which can thereby degrade the reliability of the DRAM device.
A conventional method for forming a bit line buffer pad (conductive contact) in the bit line contact hole, and for forming a storage electrode buffer pad (conductive contact) in the storage electrode contact hole will now be described. FIGS. 1 through 5 are cross-sectional views for illustrating a method for forming buffer pads (conductive contacts) of a conventional DRAM device. Portions indicated by reference characters "a" and "b" represent a cell array region and a peripheral circuit region, respectively.
Referring to FIG. 1, a trench region is formed on a predetermined area of a semiconductor substrate 1 by a conventional method, and an isolation film 3 comprising an insulating film is formed in the trench region. A gate pattern 11 is then formed, by sequentially depositing and etching a gate oxide film 5, a gate electrode 7 and a capping insulating film 9. The gate electrode 7 is used as a wordline of the DRAM device. The spacing "s" between the gate patterns 11 formed on the cell array region "a" is generally narrower than the spacing between the gate patterns 11 formed on the peripheral circuit region "b".
Next, an insulating film 13 having a predetermined thickness T1, for example, a high temperature oxide (HTO) film, is formed on the entire surface of the resultant structure. The thickness T1 is determined so that the region between the gate patterns 11 formed in the cell array region "a" is not completely filled with the high temperature oxide film 13.
FIG. 2 is a cross-sectional view for illustrating the step of forming first spacers 13b on the sidewalls of the gate patterns 11 formed in a cell array region "a". In detail, a first photoresist pattern 15 is formed for covering a peripheral circuit region "b" of the resultant structure having the insulating film 13 formed therein. Then, the insulating film 13 exposed in the cell array region "a" is anisotropically etched using the first photoresist pattern 15 as a mask. The first spacer 13b is formed with a predetermined width W1 on the sidewall of the gate pattern 11 of the cell array region "a", and an insulating film pattern 13a is formed for covering only the peripheral circuit region "b".
FIG. 3 is a cross-sectional view for illustrating the step of forming a conductive film 17 and second photoresist patterns 19a and 19b for defining a buffer pad. In detail, the first photoresist pattern 15 is removed, and then a conductive film 17 having a thickness T2, for example a doped polysilicon film, is formed on the entire surface of the resultant structure. The conductive film 17 is formed thick enough to completely fill the region between the gate patterns 11 of the cell array region "a". The thickness T2 represents the thickness of the conductive film 17 formed on the area where the interval between the gate patterns is wide. Accordingly, the actual thickness T3 of the conductive film 17 filled in the gate pattern 11 of the cell array region "a" is thicker than the thickness T2. Then, second photoresist patterns 19a and 19b are formed by conventional photolithography, to cover the conductive film 17 filled in the gate patterns 11 of the cell array region "a". The conductive film 17 having the thickness T3 is exposed in the cell array region.
FIG. 4 is a cross-sectional view for illustrating the step of forming a storage electrode pad 17a and a bitline pad 17b as buffer pads. In detail, the conductive film 17 is dry-etched using the second photoresist patterns 19a and 19b as a mask, to thereby form a buffer pad (a storage electrode pad 17a and a bitline pad 17b) for covering the source and drain regions between the gate patterns 11 of the cell array region "a". An over-etching process is preferably performed in order to completely remove the conductive film 17 having thickness T3 from the cell array region "a".
Unfortunately, the exposed insulating film pattern 13a of the peripheral circuit region becomes thinner due to the over-etching process for forming the buffer pads 17a and 17b. The reason is that the insulating film pattern 13a is also slightly etched, while the conductive film 17 is etched. As a result, the insulating film pattern 13a under the conductive film 17 formed in the peripheral circuit region "b" is etched, to thereby form an insulating film pattern 13c having thickness T1' which is smaller than the initial thickness T1.
When the initial thickness T1 of the insulating film 13 is small, the semiconductor substrate 1, including the source and drain regions of a transistor between the gate patterns 11 of the peripheral circuit region "b", may be exposed, or the semiconductor substrate 1 may be damaged by over-etching. Still referring to FIG. 4, the second photoresist patterns 19a and 19b are removed, and then a third photoresist pattern 21 for covering the cell array region "a" is formed.
FIG. 5 is a cross-sectional view for illustrating the step of forming a second spacer 13d on the sidewall of the gate pattern 11 of a peripheral circuit region "b". In detail, the insulating film pattern 13c in the peripheral circuit region "b" is anisotropically etched using the third photoresist pattern 21 as a mask, to thereby form the second spacer 13d on the sidewall of the gate pattern 11 of the peripheral circuit region "b". The width W2 of the second spacer 13d is less than width W1 of the first spacer 13b.
A first inter-dielectric layer and a bitline are then formed on the resultant structure. Then a second inter-dielectric layer, a storage electrode, a dielectric film and a plate electrode are formed, to thereby complete a DRAM cell.
As described above, according to a method for forming a conventional buffer pad, the width of second spacers formed on the sidewalls of the gate patterns of the peripheral circuit region is affected by the over-etching during formation of the buffer pads. When the insulating film is thin to begin with, the source and drain regions of a transistor in the peripheral circuit region may be damaged by the etching. The etching damage may increase the leakage current of the transistor, which may increase the power consumption of a DRAM device. Further, since the width of the second spacers is less than that of the first spacers, the effective channel length of the transistor formed in the peripheral circuit region is generally reduced, which may lead to short channel effects.